Hardware Realization of High-Speed Area-Efficient Floating Point Arithmetic Unit on FPGA

Published: 2024
2024 International Conference on Machine Intelligence and Smart Innovation (ICMISI)
ISBN/ISSN: 979-8-3503-6574-0

Abstract

Floating point representations are required in many applications due to their universality and ability to represent huge numbers accurately and in compact bit-width. Floating point arithmetic is complex, performance inefficient, and area-consuming compared to integer arithmetic operations. In this paper, hardware realization of area-efficient high-performance floating point arithmetic units for IEEE 754 floating point single precision and double precision formats on FPGA are proposed. The proposed units achieved the same accuracy as software in all tested cases and were able to produce the same chaotic behavior of the Ro¨ssler system identical to the software simulation results on MATLAB. The hardware realization of the floating point adder/subtractor occupied only 0.11% and 0.28% of AMD's KCU105 FPGA while achieving a maximum frequency of 121 MHz and 106 MHz for the single and double precision units respectively. The floating point multipliers on the other hand occupied 0.14% and 0.04% of the total area and reached a maximum frequency of 140.5 MHz and 104.8 MHz for the single and double precision respectively.